Title: Design Methodologies for Scalable and Reliable Memory Systems
Dr. Linda Milor, ECE, Chair , Advisor
Dr. Abhijit Chatterjee, ECE
Dr. Madhavan Swaminathan, ECE
Dr. Sudhakar Yalamanchili, ECE
Dr. Hao-Min Zhou, Math
The objective of this research is to develop design methodologies for scalable and reliable memory systems in the presence of scalability and reliability issues exacerbated or created by continuous scaling. After investigating the origins and device-level models of memory failures, to examine the impact of such failures on operations of a memory system, this research proposes circuit- and system-level modeling and simulation methods. With significant observations from simulation results, this research introduces design methodologies that mitigate row-hammering phenomenon by employing counter-based or probabilistic row activations and repair increasing wearout failures by exploiting error-correcting codes for the error detection and sequence of commands for error identification during field operations. To enhance the reliability of a memory system, this research proposes accurate memory reliability estimation and diagnosis methodologies using a system-level accelerated life test with a built-in self-test and error-correcting codes. This research also introduces a method of optimizing the design of experiments that isolates a failure caused by a target wearout mechanism from failures caused by other mechanisms and minimizes errors in the estimation of wearout parameters at the normal operating condition.