Title: Comprehensive Variation-aware Aging Simulator using a Unified Gate Delay Model
Dr. Linda Milor, ECE, Chair , Advisor
Dr. Sung-Kyu Lim, ECE
Dr. Azad Naeemi, ECE
Dr. Abhijit Chatterjee, ECE
Dr. Jye-Chyi Lu, ISyE
This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work lies on its statistical timing analyzer and the ability to handle the combined effect of a variety of front-end-of-line (FEOL) wearout mechanisms, while including both the manufacturing process variability and the real-time uncertainties in workload and ambient conditions like operating temperature and IR drops. Overall, the proposed framework presents the correlation between circuit performance (speed) and circuit lifetime, which enables circuit designers to avoid excessive guard-banding, by using a better understood reliability budget to achieve higher performance.