PhD Defense by Ninad Shahane





Under the provisions of the regulations for the degree




on Monday June 18, 2018

1:00 PM

in GTMI 401


will be held the





Ninad Shahane




Committee Members:


Prof. Rao Tummala, Advisor, MSE/ECE

Prof. Antonia Antoniou, Co-advisor, ME

Prof. Naresh Thadhani, MSE

Prof. Preet Singh, MSE

Dr. Vanessa Smet, ECE

Dr. Pulugurtha Raj, ECE



The need for higher I/O density, performance and miniaturization at low cost in emerging high-performance systems, with reduced power consumption, is projected to drive off-chip interconnection pitches to 20µm and below in the coming years. This aggressive pitch scaling has pushed solder-based interconnections to their material, manufacturability and reliability limits with aggravated risks of solder bridging and stress management challenges. New solutions, beyond solders, are, therefore, required to meet the performance and reliability needs of emerging electronic systems. While all-Cu interconnections have been extensively pursued as the ultimate interconnection node, direct Cu-Cu bonding faces many manufacturability and reliability challenges that prevent its applicability to high-volume manufacturing. The objectives of the proposed research are to design and demonstrate novel chip-to-package substrate Cu-based interconnections without solders at 20µm pitch for power handling at current densities exceeding 1E+05 A/cm2, high-throughput assembly, and thermomechanical reliability protecting low-K on-chip dielectrics. To realize these objectives, two approaches are proposed, based on design of nanoscale bonding interfaces for assembly throughput, and electrical, thermal and reliability performances.

The first approach utilizes novel Au-based bimetallic thin-films applied on Cu bumps and pads to prevent oxidation and enhance bonding reactivity. The Au bonding layers provide soft, oxide-free bonding interfaces, enabling assembly at lower temperatures and in air. Low-cost fly-cut planarization is considered at wafer level to eliminate bump noncoplanarities, thereby lowering bonding pressures while mitigating stresses in on-chip and on-substrate wiring layers. This approach focuses on thin-film interdiffusion in nanocrystalline Cu-Ni/Pd-Au layers and the reaction kinetics behind intermetallic compound (IMC) formation at the bonded interfaces. A high-speed thermocompression assembly process is developed and validated to boost throughput. Furthermore, the stability of these interconnection systems is demonstrated through extensive thermomechanical and electro migration reliability testing. The second approach introduces low-modulus nanocopper foam caps on bulk Cu micro-bumps to act as compliant and reactive bonding interfaces. Nanofoams are a new class of nanomaterials with current applications in catalytic sensing, energy storage and building construction. Their relatively low Young’s modulus (20-30GPa) with interconnected feature sizes of <100nm, giving high reactivity, make it also a promising material for electronics packaging. Copper nanofoams undergo coarsening and densification at low bonding temperatures to achieve bulk-like thermal and electrical characteristics under high-throughput assembly. A fundamental understanding of this sintering process is proposed and contrasted to that of conventional nanoparticle-based systems. Using co-electrodeposition techniques, patterned nano-Cu foam capped interconnections are fabricated and a first assembly of such compliant interconnections is demonstrated with preliminary reliability.


In summary, these unique Cu interconnection technologies address cost, throughput, and pitch-scaling and therefore, have the potential to become the next interconnection nodes for high-performance systems.

Event Details


  • Monday, June 18, 2018
    1:00 pm - 3:00 pm
Location: GTMI 401